1. Field of the Invention
The present invention relates to a method for manufacturing a semiconductor device, and more specifically to a method for manufacturing a semiconductor device such as a MOSFET integrated circuit having trenches having different depths.
2. Description of Related Art
With recent increase in the integration density of a semiconductor integrated circuit, further microminiaturization of circuit elements is demanded. In addition, with the microminiaturization of circuit elements, nicrominiaturization of a device isolation region is demanded and has become an important problem.
In the prior art semiconductor integrated circuit, it was a general practice to realize an inter-device electric isolation by selectively oxidizing a silicon semiconductor substrate by a LOCOS (local oxidation of silicon) process. However, when the device isolation is conducted by the LOCOS, a so-called "bird's beak" is formed in the proximity of the device isolation region in the process of manufacturing the semiconductor integrated circuit, and in order to prevent a latch-up phenomenon in a well isolation region, it was necessary to form the well isolation region having the width on the order of 7 .mu.m to 8 .mu.m to surround the well. However, these have become a structural cause for obstructing the increase of the integration density in the semiconductor integrated circuit
Under the above mentioned circumstance, it was proposed to electrically isolate between devices by forming a groove, called a "trench", and by filling up the trench with an insulating material. In this case, in order to make a well isolating region (isolation width) small, a relatively narrow and deep trench and a relative wide and shallow trench are used in combination.
Japanese Patent Application Pre-examination Publication No. JP-A-60-226126 and No. JP-A-01-232739 propose semiconductor device manufacturing methods using a device isolation technology utilizing the trench. In these methods, each device is isolated by forming trenches having different depths. In addition, it is necessary to carry out a different photoresist process for each trench having a different depth. Incidentally, an English abstract of each of JP-A-60-226126 and No. JP-A-01-232739 is available from the Japanese Patent Office and the content of each English abstract is also incorporated by reference in its entirety into this application.
First, the process disclosed by JP-A-60-226126 will be described. After a mask pattern for forming a shallow trench is formed, a photoresist is formed to cover a deep trench formation region and then patterned, and a mask layer is etched by using the patterned photoresist as a mask to form a deep trench, and thereafter, a further etching is conducted by using the mask pattern for forming the shallow trench, so as to form a shallow trench.
However, the following problems has been encountered in the above mentioned method for manufacturing the semiconductor device. Namely, the prior art method typified by the process disclosed by JP-A-60-226126 requires two photoresist processes, namely, a photoresist process for forming the shallow trench and a photoresist process for forming the deep trench. Increase of the number of photoresist processes results in increase of the number of photoresist removing processes, resulting in an increased cost for manufacturing the semiconductor device.
Japanese Patent Application Pre-examination Publication No. JP-A-60-226135 (an English abstract of JP-A-60-226135 is available from the Japanese Patent Office and the content of the English abstract of JP-A-60-226135 is incorporated by reference in its entirety into this application) proposed a semiconductor device manufacturing method capable of simplifying the process for forming the trench for the device isolation. In this proposed method, a pattern for forming a deep trench used for a well isolation, is automatically generated in a self-alignment with a well pattern. According to this proposed method, a gap is formed in a self alignment at an end of the mask pattern used for a well implantation, by a lift-off process, and then, an etching is carried out to form a trench. Thus, the deep trench used for the well isolation can be formed without increasing the number of photoresist steps.
However, even if the method disclosed by JP-A-60-226135 is used, the microfabrication of the device cannot be realized, and stability in manufacturing of the semiconductor integrated circuit device is obstructed. In brief, in this proposed method, a mask used for forming the trench having a sufficient depth to penetrate through the well in order to isolate the well, is formed by lifting off a plasma CVD insulating film on a first mask formed on a first well, by utilizing the phenomenon that a side wall of the plasma CVD insulating film is preferentially etched. However, if the spacing between the first masks becomes small because of reduction of the device size caused by the increased integration density of the semiconductor integrated circuit device, the plasma CVD insulating film no longer enters into the gaps between the first masks, with the result that a mask used for forming a trench in a second well by an etching cannot be formed.
A second problem is that, when the plasma CVD insulating film is lifted off, the peeled-off plasma CVD film is deposited again on the semiconductor substrate, disrupting the stability in manufacturing of the semiconductor integrated circuit device.